1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having memory cells with a relatively long time required for data write.
2. Description of Related Art
PRAMs (Phase change Random Access Memories) that perform data storing by using a phase change material have been proposed as a type of semiconductor memories that is an alternative to DRAMs (see Japanese Patent Application Laid-open Nos. 2006-24355 and 2005-158199). A PRAM stores data depending on a phase state of the phase change material included in a recording layer. Because an electric resistance of the phase change material in a crystalline phase is different greatly from that in an amorphous phase, data can be recorded utilizing such a difference.
The phase state is changed by applying a write current to the phase change material to heat it. Data is read by applying a read current to the phase change material to measure its resistance value. The read current is set to be far lower than the write current so that the phase is not changed. Because the phase state of the phase change material is not changed unless high temperature heat is applied, the data is not lost even when a power supply is turned off.
To amorphize (reset) a phase change material, the phase change material needs to be heated to a temperature equal to a melting point or higher by applying the write current and then cooled rapidly. To crystallize (set) the phase change material, the phase change material needs to be heated to a temperature higher than a crystallization temperature and lower than the melting point by applying the write current and then cooled gradually. Accordingly, a time required for a set operation is longer than that required for a reset operation in a PRAM.
As described above, because the time required for a set operation is different greatly from the time required for a reset operation in a PRAM, control utilizing a set pulse for performing the set operation and a reset pulse for performing the reset operation is often performed to ensure compatibility with other general purpose memories such as a DRAM.
Meanwhile, in accessing to other general purpose memories such as a DRAM, addresses are generally inputted twice in a divided manner. That is, a row address is inputted first and then a column address is inputted. According to a DRAM, for example, after a row address is inputted, different column addresses are successively inputted, thereby writing data successively. To enable such successive data write in a PRAM, a write control circuit that generates a set pulse and a reset pulse (these pulses are collectively called “write signal”) is provided for each page. The “page” represents a memory cell group the same column address is allocated to.
However, when the write control circuit is provided for each page, the circuit size is increased naturally. Particularly in a case of a semiconductor memory device with a long page length like a DRAM, the increased circuit size may lead to an increase in the chip area. Such a problem occurs not only in a PRAM but also in a semiconductor memory device including memory cells with a relatively long time required for data write.